Recently, semiconductor integrated circuits for driving liquid crystal have been improved to have more output terminals for driving liquid crystal and to output multi-value voltages in more gray scales from the output terminals, according to improvement of liquid crystal panel to be larger in size and higher in definition. For example, some of currently-most-prevalent semiconductor integrated circuits for driving liquid crystal include about 500 output terminals thereby being capable of outputting 256-gray scale voltages. Moreover, such a liquid crystal driving semiconductor integrated circuit is under development that includes 1000 or more output terminals. Moreover, as to gray scale output voltages, such a liquid crystal driving semiconductor integrated circuit is under development in response to increase in colors in the liquid crystal panels that is capable of outputting 1024 gray scales.
An arrangement of a conventional liquid crystal driving semiconductor integrated circuit is explained below referring to FIG. 27, which is a block diagram illustrating the arrangement of the conventional semiconductor integrated circuit.
The semiconductor integrated circuit 101 for driving liquid crystal illustrated in FIG. 27 is capable of outputting m-gray scale output voltages from n-number output terminals for driving liquid crystal. Firstly, the arrangement of the semiconductor integrated circuit 101 for driving liquid crystal is explained. The semiconductor integrated circuit 101 externally includes a clock input terminal 102, a gray scale date input terminal 103, a LOAD signal input terminal 104, V0 terminal 105, V1 terminal 106, V2 terminal 107, V3 terminal 108, and V4 terminal 109. The gray scale date input terminal 103 includes a plurality of signal input terminals. The V0 terminal 105, V1 terminal 106, V2 terminal 107, V3 terminal 108, and V4 terminal 109 are reference power source terminals.
The semiconductor integrated circuit 101 includes an n number of signal output terminals 111-1 to 111-n for driving the liquid crystal (hereinafter, the signal output terminals for driving the liquid crystal are referred to as the signal output terminals, and signal output terminals 111-1 to 111-n are referred to as the signal output terminals 111, collectively). Moreover, the semiconductor integrated circuit 101 includes a reference power source comparator circuit 121, a pointer shift register circuit 123, a latch circuit section 124, a hold circuit 125, a D/A converter (Digital Analog Converter: hereinafter, referred to as DAC) circuit 126, and an output buffer 127. The pointer shift register circuit 123 is constituted by n stages of shift register circuits 123-1 to 123-n. Further, the latch circuit section 124 is constituted by an n number of latch circuits 124-1 to 124-n. The hold circuit 125 is constituted by an n number of hold circuits 125-1 to 125-n. Moreover, the DAC circuit 126 is constituted by an n number of DAC circuits 126-1 to 126-n. In addition, the output buffer 127 is constituted by an n number of output buffers 127-1 to 127-n, each of which is constituted by an operational amplifier.
Next, described is how the semiconductor integrated circuit 101 is operated. The pointer shift register circuit 123 selects the latch circuits 124 sequentially from the latch, circuits 124-1 to 124-n according to the clock input signal inputted via the clock input terminal 102. The latch circuit 124 that is selected by the pointer shift register circuit 123 stores gray scale output data supplied from the gray scale data input terminal 103. The gray scale output data is data to be supplied to the corresponding one of the latch circuits 124, that is, to the corresponding one of the signal output terminals 111, and is in synchronism with the clock input signal. Therefore, the latch circuits 124-1 to 124-n can store gray scale output data of different values for the signal output terminals respectively corresponding to the latch circuits 124-1 to 124-n. The gray scale output data stored in the latch circuits 124-1 to 124-n is forwarded to the corresponding hold circuit 125-1 to 125-n respectively. Further, the hold circuits 125-1 to 125-n receives the gray scale output data and then output the gray scale output data to the DAC circuits 126-1 to 126- as digital data.
The DAC circuits 126-1 to 126-n respectively select one voltage value among gray scale voltages of m levels, based on the gray scale output data respectively supplied from the corresponding hold circuits 125. Then, the DAC circuits 126-1 to 126-n each output the selective voltage value to the output buffer 127-1 to 127-n respectively. The DAC circuits 126 can output the gray scale voltages of m levels according to the voltage inputted respectively via the reference power source V0 terminal 105 to V4 terminals 109. Next, the output buffers 127 buffer the gray scale voltages respectively supplied from the DAC circuits 126, and then output the buffered voltages to the corresponding signals output terminals 111 as liquid crystal panel driving signals.
As described above, the shift register circuits 123, the latch circuits 124, hold circuits 125, DAC circuits 126, and output buffers 127 are necessary as many as the liquid crystal driving signal output terminals 111. If 1000 of the liquid crystal driving signal output terminals are provided, 1000 each of the circuits 124 to 127 should be necessary.
As described above, the display apparatus such has liquid crystal panels have been improved to be large in size and higher in definition. As a result, a full-spec high definition television (HDTV) has 1920 data lines. As the display driving semiconductor integrated circuits should provide gray scale voltage signals for each of RGB, the display driving semiconductor integrated circuits should have 5760 (1920×3) outputs, in other words, 5760 signal output terminals for driving the liquid crystal. If one display driving semiconductor integrated circuit had 720 outputs, 8 display driving semiconductor integrated circuit s should be necessary.
In general, the display driving semiconductor integrated circuit is tested while it is still in the wafer form, and then subjected to pre-shipment test after packaging. Then, the display driving semiconductor integrated circuit is subjected to display test after being mounted on a liquid crystal panel. Furthermore, the display driving semiconductor integrated circuit is subjected to screening test in terms of burning-in and stress. Thereby, a display driving semiconductor integrated circuit that may cause a defect in an initial stage is omitted. This eliminate a possibility of shipping, to a market, a display apparatus with a display driving semiconductor integrated circuit that may cause display defect. However, in rare cases, a display defect would happen in use of the display apparatus due to a very minor defect or contamination, which is not judged as being defect in the pre-shipment test or the screening test. For example, even if a possibility of display defect after the shipment is 0.01 ppm (one in hundred millions) per data line in the display driving semiconductor integrated circuit, a full-spec HDTV having 5760 data lines has a possibility of display defect of 57.6 ppm (57.6 in hundred millions). That is, about one HDTV in 17361 HDTVs causes a display defect. Thus, an apparatus large in size and higher in definition has a higher possibility of causing a display defect.
Such a display apparatus with a display defect should be collected promptly in order that its defective display driving semiconductor integrated circuit may be healed from a defect. This collection not only requires a large cost but damages a brand image of the display apparatus.
A conventional art discloses an art that a display driving semiconductor integrated circuit includes a spare circuit for replacing a defective circuit, so that the display driving semiconductor integrated circuit can avoid from being defective by replacing the defective circuit with the spare circuit.
Specifically, Patent Document 1 discloses an art in which a display driving semiconductor integrated circuit includes spare circuits each of which is in parallel with corresponding one of stages of a shift register, and the display driving semiconductor integrated circuit performs self-inspection to inspect the shift register selects either one of each said parallel circuit. Furthermore, Patent Document 2 discloses a method including providing a selector at each of input and output of DAC circuits and switching over the selector according to information in a RAM in which a position of a defective DAC circuit is stored, so as to select non-defective circuits to use.
[Patent Document 1]
    Japanese Unexamined Patent Application Publication, Tokukaihei, No. 6-208346 (published on Jul. 26, 1994)[Patent Document 1]    Japanese Unexamined Patent Application Publication, Tokukaihei, No. 8-278771 (published on Oct. 22, 1996)